The present invention relates to the field of metrology, and more particularly, to targets and measurement of very small features, on the scale of device features and quantized substructures.
According to the ITRS (International Technology Roadmap for Semiconductors), the 5 nm technology node will be ramping in about 5 years. Such device dimensions deviate considerably from the typical dimensions of structures used to form targets for overlay metrology. The dimensions of target structures are typically in the 100-1000 nm range. This two orders of magnitude gap leads to a significant bias of a few nanometers between overlay measured on a device and overlay measured from a target. The control budget at these advanced nodes will be just a couple of nanometers, and this target-device bias is becoming a huge issue which prohibits overlay control based on the current methodology.